The transistor is the basic building block of all present day integrated circuit (IC) designs and devices. Fundamentally, a transistor is an electronic switch which includes a source region, a drain region electrically insulated from the source, and a control gate. A control voltage applied to the gate electrode selectively controls electrical communication between the source and drain electrodes, thereby controlling the binary (“on” and “off”) state of the device.
A common integrated circuit implementation involves interconnecting a large number of field effect transistors (FETs), typically metal oxide semiconductor field effect transistors (MOSFETs), resulting in a highly complex, three dimensional integrated circuit device. The mechanical and electrical integrity of the source, drain, and gate electrodes of these transistors can significantly impact device performance, device variation, and manufacturing yield.
As the number and complexity of functions implemented in IC devices (such as microprocessors and memory devices) increases, more and more transistors must be incorporated into the underlying integrated circuit chip. The fabrication of large scale integrated circuit devices presents a number of competing manufacturing and processing challenges.
Presently known methods for interconnecting the many transistors that make up the finished integrated circuit include patterning contact trenches into the surface of an insulating layer, and filling the trenches with copper to form conductive interconnects. Copper is disadvantageous in that it tends to migrate along boundaries between the layers of dielectric material that electrically isolate the various interconnecting levels from one another. Copper electromigration can be mitigated by adding certain metallurgical additives, or dopants (alloying elements), to the main copper interconnect body. However, this adds complexity and cost to the metallization procedure, and may not be feasible for some dopants.
Accordingly, a need exists to provide methods for fabricating MOSFET ICs on a silicon substrate with conductive interconnecting layers having a desired dopant amount in a manner which is flexible and cost efficient. Furthermore, other desirable features and characteristics of various embodiments will become apparent from the subsequent summary, detailed description, and the appended claims, taken in conjunction with the accompanying drawings, brief description of the drawings, the foregoing technical field and this background of the invention.